The present invention relates to memory devices and methods of operation thereof and, more particularly, to memory module systems and methods of operation thereof.
Conventional memory devices used in personal computers, notebook computers and other devices are typically organized in a modular fashion. In particular, a desktop or notebook computer may include one or more memory modules, each of which includes a plurality of memory device chips mounted on a circuit substrate (e.g. a printed circuit board) that further includes a connector configured to mate with bus connector on the computer's motherboard. Conventional memory modules may have a variety of different configurations, such as UDIMM (Unbuffered Dual In-line Memory Module), RDIMM (Registered Dual In-line Memory Module) and FBDIMM (Fully Buffered Dual In-line Memory Module).
FIG. 1 illustrates a conventional UDIMM 100. The UDIMM 100 includes a circuit substrate 110 and a plurality of memory devices 120 disposed thereon. The memory devices 120 are controlled by a memory controller 160 external to the UDIMM 100. As shown, the memory controller 150 and each of the memory devices 120 may be coupled in common to a control/address (C/A) bus 130 and a clock line 140, while respective bidirectional data busses 150 extend between the respective memory devices 120 and the memory controller 160. In such an arrangement, more memory devices are coupled to the C/A bus 130 and the clock bus 140 than to the data busses 150. Consequently, the C/A bus 130 and the clock bus 140 may have a greater loading than the data busses 150.
One conventional technique to reduce control/address line loading between a memory controller and memory module is to provide point-to-point links between a memory controller and memory modules by buffering C/A, clock and/or data signals on the memory modules. For example, FIG. 2 illustrates a conventional RDIMM 200 that provides clock and C/A signal buffering. The RDIMM 200 includes a plurality of memory devices 220, a C/A buffer 222, and a clock buffer (e.g., a phase-locked loop circuit) 224 disposed on a circuit substrate 210. Respective data busses 250 extend between respective ones of the memory devices 220 and an external memory controller 260, similar to a UDIMM. A single C/A bus 230 extends between the memory controller 260 and the C/A buffer 222. A C/A sub-bus 226 on the module 200 couples the C/A buffer 222 and the memory devices 220. Similarly, a single clock bus 240 extends between the memory controller 260 and the clock buffer 224, and a clock sub-bus 228 couples the clock buffer 224 to the memory devices 220. In such an arrangement, the loading of the data busses 250, the C/A bus 230 and the clock bus 240 may be roughly equivalent, but the sub-busses 226, 228 of the module 200 may have relatively higher loading in comparison to the data busses 250. In an FBDIMM, data may be similarly buffered.
Memory architectures employing high-speed serial communications between memory modules and a memory controller have recently been developed. For example, the Advanced Memory Buffer (AMB) memory architecture employs high-speed serial communications links that connect a memory controller to a plurality of FBDIMMs in a cascaded arrangement. Typically, each of the FBDIMMs is configured to pass data and control signals downstream (away from the memory controller) and upstream (towards the memory controller). The use of high-speed serial links can reduce the number of signal lines required to link a memory module to a memory controller, which can simplify circuit board wiring and/or increase performance. U.S. Pat. No. 6,502,161 to Perego et al. describes a buffered memory system topology in which a point-to-point link between a master and one or more memory subsystems. Each subsystem includes a buffer device that mediates between the master and memory devices of the subsystem, and respective groups of memory devices may be coupled to the buffer device by respective channels that each include control lines, data lines and clock lines.